About the role
Senior/Staff IO/ESD Layout Engineer responsible for implementing custom layout of various IP blocks, handling floorplanning, layout construction, verification, and QA sign‑off, while providing project updates and effective communication.
FablessOnsiteChip Design
Key Responsibilities
- Undertake the roles of a custom layout engineer in realizing the physical implementation of a variety of circuitries, including Foundation IP (Standard Cells, Memory Compilers, IO/ESD), Analog IP, and RF building blocks.
- Own tasks assigned and assume full responsibility of the complete layout
Requirements
- Passion for innovation in microchip design and advanced semiconductor technology.
- Proficiency in custom layout techniques for integrated circuits.
- Ability to drive physical implementation across diverse IP types.