About the role
MediaTek is seeking a Senior Custom Layout Engineer to join the Custom Layout engineering team, responsible for physical design implementation of Foundation IP, Analog IP, and RFIC for advanced process platforms and SoC developments. The role involves layout design, automation, APR, and collaboration with multi-functional teams to deliver high-quality IPs and test-chips.
FablessOnsiteChip Design
Key Responsibilities
- Undertake the role of layout engineer for day-to-day project execution of a variety of layout design implementation, including but not limited to Layout Automation, APR for digital design, Workflow Scripting, Foundation IP (IO/ESD), Analog IP and RFIC, across multiple process nodes and diversified foundries.
- Collaborate with process-oriented or project-oriented multi-functional teams in delivering the physical design portion of IP, test-chip, RFIC or SoC.
- Be the DRI (Directly Responsible Individual) for the tasks assigned and assume full responsibility of the complete layout implementation process, including floorplanning layout construction, physical verification and QA flow sign-off.
- Be the DRI for layout automation flow, including APR layout implementation and sign-off, layout automation utility development, enhancement and flow sign-off.
- Provide timely project status updates and proactively anticipate and mitigate potential execution pitfalls to ensure smooth and high-quality delivery for each project.
- Be proactive in communicating effectively with multi-functional teams and multi-site to constantly optimize layout for better Power, Performance & Area.
- Achieve good quality layout, work efficiently and effectively with schedule in mind.
Requirements
- Candidates with proven track record and deep technical skills will be considered for mid-level position.