About the role
The Multi-Dies Physical Verification Engineer is responsible for sign‑off of 3D IC designs, collaborating with package, ESD, and chip verification teams to resolve integration issues and improve tape‑out efficiency through automation and reporting.
FablessOnsiteChip Design
Key Responsibilities
- Responsible for Multi-Dies Physical Verification Sign-off in area of (3D_Stack, 3D_PERC, 3D_ANT) for tape-out
- Co-work with Package Design Team to resolve Multi-Dies integration issues
- Co-work with ESD Team to run 3D_PERC flow
- Coordinates with Chip PV Team on active dies related issues (DRC, LVS, ANT, ERC, ESD)
- Provide automation solutions to improve efficiency in tape-out flow
- Report on Tapeout PV issues
Requirements
- Experience with Multi-Dies and 3D IC physical verification.
- Familiarity with advanced sign-off checks (DRC, LVS, ANT, ERC, ESD).
- Ability to coordinate complex flows between various design teams.