About the role
The Chip Physical Verification Engineer is responsible for full‑chip sign‑off across multiple verification domains for SOC tape‑out, collaborating with place‑and‑route, IP, and manufacturing teams, and developing automation to streamline the flow.
FablessOnsiteChip Design
Key Responsibilities
- Responsible for Full‑chip Physical Verification Sign‑off in area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape‑out
- Co‑work with Place & Route team to resolve full‑chip
Requirements
- Proven experience in advanced technology node physical verification.
- Expertise in sign-off checks (DRC, LVS, ANT, ERC, ESD, PERC).
- Ability to enable and define physical sign-off flows for SOC design.