About the role
The Senior STA Lead will drive static timing analysis strategy and execution for advanced 3GHz+ CPU projects, owning the sign-off process and collaborating with cross-functional teams to ensure first-time-right silicon. Responsibilities include hands-on execution, methodology development, timing closure, and technical leadership.
FablessOnsiteChip Design
Key Responsibilities
- Oversee and ensure full-chip and block-level STA sign-off using industry-standard tools (PrimeTime, PrimeClosure), and establish sign-off criteria and checklists.
- Define, develop, and implement advanced timing analysis methodologies and flows, including OCV/POCV, MMMC, hierarchical timing, and sign-off automation.
- Guide the team in resolving complex timing closure challenges, including high-frequency datapaths, complex clocking schemes, and asynchronous domains.
- Work closely with Architecture, RTL, DFT, Analog, and Physical Design teams to provide early feedback on micro-architecture, timing budgets, and power/area trade-offs.
- Lead technical reviews, sign-off readiness assessments, and risk mitigation planning.
- Drive the use of scripting (TCL, Python) to automate timing analysis, ECO generation, and QoR tracking.
Requirements
- Deep expertise in Static Timing Analysis (STA) for high-speed designs.
- Proficiency with industry-standard EDA tools (e.g., PrimeTime).
- Strong ability to drive timing closure and manage cross-functional dependencies.