About the role
The Senior/Staff Physical Verification CAD Engineer collaborates with PDK and QA teams to develop and maintain rule decks and verification flows, performs full-chip verification, and creates automation scripts to improve design quality.
FablessOnsiteChip Design
Key Responsibilities
- Co-work with PDK team to code and maintain DRC/LVS/ANT/ERC/LPE/ESD rule deck for various processes
- Develop layout implementation flow and physical verification flow
- Co-work with QA team to reduce the PDKs/Rule deck defects
- Perform full-chip physical verification such as debugging DRC/LVS/ERC
- Implement automation scripts in C-shell, Python and Perl
Requirements
- Expertise in physical verification flows and sign-off checks.
- Proficiency in scripting languages (C-shell, Python, Perl) for automation.
- Ability to work closely with PDK teams on rule deck maintenance.