About the role
The Senior/Staff Physical Design Engineer will lead physical design of advanced 6nm‑4nm chips, coordinate block synthesis and verification, manage hierarchical floorplanning for large designs, and oversee PD schedule and tapeout delivery.
FablessOnsiteChip Design
Key Responsibilities
- IC physical design of 6nm/4nm/3nm and below world leading advanced process chip, from RTL to GDS.
- Block coordinator role for Synthesis/APR/PV tasks of more than 10 blocks, solving the critical issue and give the solution to block owners.
- TOP role for the complicated hierarchical chip (more than 20 million instances plus 1000+ macros), doing floorplan, partition and assembly etc.
- PD PM role to coordinate with Frontend and Signoff team about on time delivery of the SoC PD tasks, responsible for full chip PD schedule and tapeout.
Requirements
- Expertise in advanced node physical design flows
- Strong understanding of chip-level signoff procedures
- Ability to manage complex, large-scale physical designs