VIS

Engineer ( Yield Enhancement ) (Ref: 241000072)

VIS
Foundry OperationsSingaporeOnsitePosted 6 days ago

About the role

Engineer responsible for yield enhancement and defect reduction in a front‑end semiconductor fab, supervising associate engineers, operating analysis tools, and driving continuous improvement.

FoundryOnsiteIntegration

Key Responsibilities

  • Supervise YE Associate Engineers and wafer tech operators for 24/7 inline shift operations
  • Train and certify associate engineers on recipe creation and defect source knowledge
  • Maintain and enhance SOP/OCAP and support internal/external audits
  • Operate FIB, SEM, EDX, and optical microscopy for inline failure analysis
  • Create and run recipes in Brightfield, Darkfield and other defect inspection tools
  • Perform partition analysis on defect sources and generate detailed reports

Requirements

  • Master's or Bachelor's degree in Electrical/Electronic Engineering, Material Science, Chemical Engineering, or Physics
  • 2–8 years of relevant fab experience in high‑volume semiconductor manufacturing
  • Familiarity with front‑end wafer fab processes and defect analysis
  • Strong interpersonal and communication skills
  • Demonstrated leadership capability and ability to manage a team
  • Effective team player