About the role
Senior Engineer, Analog Layout is a active engineering role at Marvell in Singapore. Open the role to review the official description and apply on the company site.
FablessOnsite
Key Responsibilities
Responsibilities are not available for this post.
Requirements
- Fin-FET is preferred
- Have a high level of proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. reports
- Possess high-level proficiency/knowledge of Synopsys or CADENCE layout entry tools
- Programming skills in any of the following are a plus: Skill or Ample or Perl, etc.
- Strong technical and analytical background, problem solving skills, etc.
- The candidate must have a proven record of laying out high-performance analog circuits in state-of-the-art CMOS process technologies, successfully performed top-level integrations, and placed products into volume production multiple times.
- Proficient in spoken and written English