About the role
Analog Layout Engineer at Marvell responsible for analog circuit layout, simulation, verification, and collaboration with global teams across multiple regions.
FablessOnsite
Key Responsibilities
- Run simulations and verifications using Cadence Virtuoso
- Collaborate closely with designers to refine and debug layouts
- Participate in routine meetings as a technical mentor and layout team member
- Provide status updates and present issues/solutions to global teams
- Own full development cycle including floorplan, layout, verification, delivery, and support
- Engage in continuous learning and knowledge‑sharing with colleagues
Requirements
- Fundamental understanding of electrical concepts, typically through a degree in Electrical Engineering (undergraduate or graduate)
- Proficiency with CAD tools, specifically Cadence Virtuoso, for implementation of microelectronic layers
- Track record of delivering high‑speed or precision analog circuits, preferably across multiple process nodes
- Experience owning the full development cycle: floorplan, layout, verification, delivery, and support
- Strong communication skills for status updates, presentations to global teams, and information sharing
- Ability to assume increasing responsibility from cells to functional blocks, macros, and full chips