About the role
Senior Engineer responsible for physical design of advanced semiconductor chips, handling place‑and‑route, timing, power integrity, and sign‑off activities using industry EDA tools.
FablessOnsite
Key Responsibilities
- Work with a global team on physical design of complex chips
- Run RTL code through synthesis and place‑and‑route tools to create the physical view
- Perform static timing analysis using tools such as Tempus or PrimeTime
- Conduct EM/IR and crosstalk analysis using Voltus or PrimeRail
- Verify power grid robustness and perform sign‑off checks
- Review completed runs for errors and create optimizations
Requirements
- Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or related field
- 3+ years of experience in physical design with focus on block‑level place‑and‑route for advanced