About the role
Senior /Lead Research Engineer (FOWLP/2.5D/3D package integration) (HI), IME role based on the published job description. Key responsibilities and requirements were extracted directly from the posting for quick review.
ResearchOnsiteInstitute of Microelectronics
Key Responsibilities
- This role is pivotal in advancing the state-of-the-art advanced packaging platform technologies, such as 2.5D/3D IC and Co-packaged optics.
- Development of critical modules includes fine pitch multi-layer redistribution layers (RDL), micro bumping, Temporary bonding and debonding process flow, flip chip thermal compression bonding, chip-to-wafer and wafer-to-wafer fusion/hybrid bonding capabilities, developing fan-out wafer level packaging, 2.5D interposer, and 3D chip stacking process integration flows for Heterogeneous Integration of chiplets.
- The position provides an exciting opportunity to contribute to groundbreaking technologies and collaborate with a dynamic team of researchers and external ecosystem stakeholders Develop advanced packaging technology platforms (fan-out packaging, 2.5D interposer and 3D stacking) capabilities and novel process integration approaches for heterogeneous chiplets integration.
- Work with design and process module teams to establish design rules and PDK for advanced packaging technologies.
- Lead capability development projects for internal and external industry projects involving new materials, advanced process integration approaches, and new test vehicle designs with minimum manageable risks.
- Engage and manage internal and external stakeholders for project activities execution and provide timely updates on schedule and deliverables.
Requirements
- Customer/partner engagement: ability to present technical content to customers and senior stakeholders; drive joint development (JDP/NRE).
- Should be able to work hands-on in the cleanroom and learning new processes and metrology equipments
- 5-10 years of experience in semiconductor experience with expertise in Cu backend integration and exposure to advanced packaging technologies (flip-chip, FOWLP, 2.5D/3D, TSV, hybrid/fusion bonding).
- Broad hands-on knowledge of one or more unit processes—such as lithography, etch (damascene, TSV via-last/middle); deposition (ALD/CVD/PVD, including high-AR barrier and seed layers); electroplating and alternative via-fill materials, CMP for hybrid bonding; fusion/hybrid bonding; wafer thinning; and dicing—is preferred.
- Proven ability to work effectively in a diverse, matrixed environment and collaborate with cross-functional departments.
- Strong analytical/problem-solving skills (Ishikawa, Seven Basic Quality Tools, brainstorming) and proficiency with DOE and SPC (JMP/Minitab).