About the role
Senior/Lead Research Engineer responsible for owning, optimizing, and sustaining wafer‑level bonding processes in a semiconductor fab, driving SPC governance, yield improvement, defect reduction, and cross‑functional collaboration for advanced packaging technologies.
ResearchOnsiteInstitute of Microelectronics
Key Responsibilities
- Own and maintain SPC control strategies for bonding processes across multiple toolsets
- Define critical process parameters (CPPs) and critical quality attributes (CQAs) such as alignment accuracy, bond strength, defectivity, warpage, and thickness
- Establish and optimize control limits, reaction plans, and process windows
- Drive yield enhancement through data analytics
- Statistical modeling
Requirements
- Serve as the process owner for bonding toolsets, including recipe setup, qualification, matching, and continuous improvement.
- Process Qualification Packages
- Bachelor's degree in Materials Science, Chemical, Mechanical, Electrical Engineering, or related fields.
- 3+ years of hands‑on experience in wafer bonding, advanced packaging, 3D integration, or related semiconductor process engineering.
- Practical experience with hybrid wafer bonding, direct bonding, and/or Temporary Bonding & Debonding (TBDB) equipment.
- Familiarity with bonding‑related metrology such as IR inspection, SAM, profilometry, bond‑strength measurement, overlay/alignment metrology, and thickness mapping.