About the role
ENGINEER, PACKAGE DEVELOPMENT ENGINEERING, PACKAGE SILICON INTEGRATION role based on the published job description. Key responsibilities and requirements were extracted directly from the posting for quick review.
IDMOnsiteAssembly & Test
Key Responsibilities
- Support chip‑package interaction (CPI) assessments by collecting data, performing basic analysis, and documenting results under guidance from senior engineers.
- Assist package design, scribe design, and assembly engineers in investigating wafer dicing, singulation, and integration topics.
- Participate in DFMEA / PFMEA activities by helping prepare inputs, reviewing risk items, and tracking action items.
- Work with wafer fab, R&D, and manufacturing teams to support yield, quality, and manufacturability issue investigations.
- Support execution of test vehicles and DOEs , including data collection, basic analysis, and report preparation.
- Learn Micron's package and silicon development flows, design rules, and change‑management processes.
Requirements
- Education & Experience Bachelor's or Master's degree in Engineering (Mechanical, Materials Science, Electrical, Chemical, or related discipline).
- < 2 years of relevant experience , including internships, co‑op programs, or research experience in semiconductor, materials, or manufacturing fields.
- Technical & Professional Skills Fundamental understanding of semiconductor manufacturing and/or packaging concepts (coursework or internship level).
- Exposure to structured problem‑solving methods (FMEA, DOE, data analysis) through academics or internships.
- Ability to follow defined engineering procedures, analyze straightforward technical problems, and learn from feedback.
- Strong attention to detail and willingness to learn new tools, processes, and technologies.