Micron Technology

Central Yield Engineer (Central YE) – Senior Engineer / Engineer

Micron Technology
Integrated Device ManufacturingSingapore, SingaporeOnsitePosted 2 months ago

About the role

Central Yield Engineer (Central YE) – Senior Engineer / Engineer role based on the published job description. Key responsibilities and requirements were extracted directly from the posting for quick review.

IDMOnsiteFront End

Key Responsibilities

  • Drive E2E yield improvement initiatives across FE wafer fabrication, probe, assembly, and final test through deep data analysis and technical insight, with primary ownership from a Central YE perspective.
  • Lead global yield analytics and learning loops, connecting FE process data, electrical/parametric test results, and AT test outcomes to rapidly identify root causes and improvement opportunities.
  • Define and execute yield strategies to ensure FE process readiness and robustness are fully aligned and qualified to support downstream AT performance and overall product yield.
  • Serve as a technical integrator across FE–AT boundaries, working with cross-functional teams to close gaps in yield, quality, and test coverage.
  • Lead or actively participate in cross-site taskforces to resolve critical yield and quality excursions, ensuring timely containment, root cause identification, and sustainable corrective actions.
  • Apply strong statistical and data-driven problem-solving techniques to large, complex manufacturing and test datasets to support decision-making and executive communication.

Requirements

  • Solid knowledge of semiconductor manufacturing and yield engineering, including FE wafer fabrication processes, electrical/parametric test, probe yield, and AT test fundamentals.
  • Strong experience in E2E data analysis, correlating FE process data with probe and final test results to drive yield and quality improvements.
  • Hands-on capability in statistical analysis, data mining, root cause analysis, and problem solving, with strong attention to detail.
  • Experience with DRAM device operation, test flows, and yield learning methodologies is highly desirable.
  • Exposure to FE integration, advanced packaging, AT processes, or test development is a plus.
  • Excellent written and verbal communication skills, with the ability to clearly explain complex technical issues to cross-functional and global audiences.